Processor throughput performance continues to increase with not just faster clock speeds that allow more operations per second, but with increasing numbers of parallel cores performing operations. The increased ability of a processor to perform more operations per second puts pressure on the interfaces to get instructions and data in and out of the processor with higher throughput to utilize the processor's performance capabilities. One primary exchange for the processor is with memory, which stores data used for the execution of operations, and stores the operation results. One mechanism to continue to exchange data between the processor and the memory is to increase the clock speed of the signaling used to exchange the data.
However, at data rates greater than approximately 3200 MT/s (mega-transfers per second), signal degradation due to inter symbol interference (ISI) is expected to increase. Additionally, the data eye at memory device connectors to the data bus is expected to be closed with non-point to point, single-loading configurations. The data eye refers to average phase of the rising and falling edges of signals sent across the signal lines interconnecting the devices. The data eye should have a consistent gap where transitioning of the input/output (I/O) signaling does not occur. Closure of the data eye refers to a scenario where the timing and voltage margins are tight enough that certain interference conditions can cause inconsistency in the signaling, making the average time of rising edges so close to the average time of falling edges to be too close to correctly sample and distinguish a signal bit. Thus, the data eye can be said to be “collapsed” when signaling transitioning occurs within the space that should not have signal transitioning. Since the memory channel data bus is expected to be very reflective due to the many impedance mismatched points that exist along the memory subsystem, ISI due to reflections is expected to increase.
Traditional methods of training or characterizing an I/O interface involve sending data from the host to the memory, and then reading the data back. Traditional testing or training involved the host or a host component, such as a memory controller, issuing write commands for the data to be sent, which the memory device would then store in the memory array. The host would then issue subsequent read commands for the data, which would then have to be retrieved from the memory array. Such a loopback procedure involves significant delays each time the memory array is accessed. Additionally, such a conventional approach may require refresh of the data in the memory array.
The loopback process would typically be iterated multiple times with different phase settings (based on different settings for voltages, currents, termination, phase compensation (e.g., delay locked loops), and other settings, or a combination) until signaling settings are determined that can meet an expected bit error rate (BER). BER goals may be on the order of 10−16 or 10−18 or better. Given such error rates, it has become impractical to generate and store the required amount of data in a memory to generate the required meaningful statistical data to determine the settings needed to meet the performance requirements. Thus, traditional methods of characterizing the receiver using the data eye or the input eye mask are insufficient for upcoming signaling targets.
Descriptions of certain details and implementations follow, including non-limiting descriptions of the figures, which may depict some or all examples, and well as other potential implementations.